View MBM29F200BA12_4624809.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ds05-20813-3e fujitsu semiconductor data sheet flash memory cmos 2m (256k 8/128k 16) bit mbm29f200ta -70/-90/-12 /mbm29f200ba -70/-90/-12 n features single 5.0 v read, write, and erase minimizes system level power requirements compatible with jedec-standard commands uses same software commands as e 2 proms compatible with jedec-standard world-wide pinouts 48-pin tsop (package suf?: pftn ?normal bend type, pftr ?reversed bend type) 44-pin sop (package suf?: pf) minimum 100,000 write/erase cycles high performance 70 ns maximum access time sector erase architecture one 16k byte, two 8k bytes, one 32k byte, and three 64k bytes. any combination of sectors can be concurrently erased. also supports full chip erase. boot code sector architecture t = top sector b = bottom sector embedded erase algorithms automatically pre-programs and erases the chip or any sector embedded program algorithms automatically write and veri?s data at speci?d address data polling and toggle bit feature for detection of program or erase cycle completion ready/busy output (ry/by ) hardware method for detection of program or erase cycle completion. ?ow v cc write inhibit 3.2 v hardware reset pin resets internal state machine to the read mode sector protection hardware method disables any combination of sectors from write or erase operations temporary sector unprotection hardware method temporarily enable any combination of sectors from write or erase operations erase suspend/resume suspends the erase operation to allow a read in another sector within the same device embedded erase tm and embedded program tm are trademarks of advanced micro devices, inc.
2 mbm29f200ta -70/-90/-12 /mbm29f200ba -70/-90/-12 n package 48-pin plastic tsop 44-pin plastic sop marking side (fpt-48p-m19) (fpt-48p-m20) (fpt-44p-m16) marking side marking side
3 mbm29f200ta -70/-90/-12 /mbm29f200ba -70/-90/-12 n general description the mbm29f200ta/ba is a 2m-bit, 5.0 v-only flash memory organized as 256k bytes of 8 bits each or 128k words of 16 bits each. the mbm29f200ta/ba is offered in a 48-pin tsop and 44-pin sop packages. this device is designed to be programmed in-system with the standard system 5.0 v v cc supply. a 12.0 v v pp is not required for write or erase operations. the device can also be reprogrammed in standard eprom programmers. the mbm29f200ta/ba is erased when shipped from the factory. the standard mbm29f200ta/ba offers access times between 70 ns, 90 ns and 120 ns, allowing operation of high-speed microprocessors without wait states. to eliminate bus contention the device has separate chip enable (ce ), write enable (we ), and output enable (oe ) controls. the mbm29f200ta/ba is pin and command set compatible with jedec standard 2m-bit e 2 proms. commands are written to the command register using standard microprocessor write timings. register contents serve as input to an internal state-machine which controls the erase and programming circuitry. write cycles also internally latch addresses and data needed for the programming and erase operations. reading data out of the device is similar to reading from 12.0 v flash or eprom devices. the mbm29f200ta/ba is programmed by executing the program command sequence. this will invoke the embedded program algorithm which is an internal algorithm that automatically times the program pulse widths and veri?s proper cell margin. typically, each sector can be programmed and veri?d in less than 0.5 seconds. erase is accomplished by executing the erase command sequence. this will invoke the embedded erase algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. during erase, the device automatically times the erase pulse widths and veri?s proper cell margin. a sector is typically erased and veri?d in 1 second (if already completely preprogrammed.) this device also features a sector erase architecture. the sector mode allows each sector to be erased and reprogrammed without affecting other sectors. the device features single 5.0 v power supply operation for both read and write functions. internally generated and regulated voltages are provided for the program and erase operations. a low v cc detector automatically inhibits write operations on the loss of power. the end of program or erase is detected by data polling of dq 7 , by the toggle bit feature on dq 6 , or the ry/by pin. once the end of a program or erase cycle has been completed, the device internally resets to the read mode. fujitsu's flash technology combines years of eprom and e 2 prom experience to produce the highest levels of quality, reliability and cost effectiveness. the mbm29f200ta/ba memory electrically erases the entire chip or all bits within a sector simultaneously via fowler-nordhiem tunneling. the bytes/words are programmed one byte/word at a time using the eprom programming mechanism of hot electron injection.
4 mbm29f200ta -70/-90/-12 /mbm29f200ba -70/-90/-12 n flexible sector-erase architecture one 16k byte, two 8k bytes, one 32k byte, and three 64k bytes individual-sector, multiple-sector, or bulk-erase capability individual or multiple-sector protection is user de?able. 3ffffh 3bfffh 39fffh 37fffh 2ffffh 1ffffh 0ffffh 00000h 16k byte 8k byte 8k byte 32k byte 64k byte 64k byte 64k byte mbm29f200ta sector architecture 3ffffh 2ffffh 1ffffh 0ffffh 07fffh 05fffh 03fffh 00000h 64k byte 64k byte 64k byte 32k byte 8k byte 8k byte 16k byte mbm29f200ba sector architecture ( 8) 1ffffh 1dfffh 1cfffh 1bfffh 17fffh 0ffffh 07fffh 00000h ( 16) 1ffffh 17fffh 0ffffh 07fffh 03fffh 02fffh 01fffh 00000h ( 16) ( 8)
5 mbm29f200ta -70/-90/-12 /mbm29f200ba -70/-90/-12 n product selector guide n block diagram family part no. mbm29f200ta/ba ordering part no. ?0 ?0 ?2 max. address access time (ns) 70 90 120 max. ce access time (ns) 70 90 120 max. oe access time (ns) 30 35 50 v ss v cc we ce a 0 to a 16 oe erase voltage generator dq 0 to dq 15 state control command register program voltage generator low v cc detector x-decoder y-decoder cell matrix y-gating chip enable output enable logic data latch input/output buffers stb stb timer for ry/by buffer ry/by reset byte a -1 address latch program/erase
6 mbm29f200ta -70/-90/-12 /mbm29f200ba -70/-90/-12 n connection diagrams a 3 a 2 n.c. a 1 a 15 a 14 reset a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 oe dq 7 dq 6 dq 5 dq 14 dq 13 dq 12 dq 1 dq 0 a 0 a 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 44 43 42 41 mbm29f200ta/mbm29f200ba standard pinout tsop fpt-48p-m19 (marking side) a 13 a 12 n.c. 17 18 19 20 36 35 34 33 40 39 38 37 v ss v ss v cc ry/by we 21 22 23 24 48 47 46 45 n.c. n.c. n.c. n.c. 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 41 42 43 44 45 46 47 48 29 30 31 32 mbm29f200ta/mbm29f200ba reverse pinout fpt-48p-m20 (marking side) 8 7 6 5 37 38 39 40 33 34 35 36 4 3 2 1 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 32 31 30 29 28 44 43 42 41 36 35 34 33 40 39 38 37 27 26 25 24 23 reset n.c. n.c. a 7 a 6 a 5 a 4 sop fpt-44p-m16 ce a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 we oe ry/by dq 7 dq 6 dq 12 dq 4 v cc a 0 a 1 a 2 a 3 dq 3 dq 2 dq 1 dq 0 v ss (top view) byte dq 15 /a -1 dq 4 dq 11 dq 3 dq 10 dq 2 dq 9 dq 8 ce oe dq 7 dq 6 dq 5 dq 14 dq 13 dq 12 dq 1 dq 0 a 0 a 16 v ss v ss v cc byte dq 15 /a -1 dq 4 dq 11 dq 3 dq 10 dq 2 dq 9 dq 8 ce a 3 a 2 n.c. a 1 a 15 a 14 reset a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 13 a 12 n.c. ry/by we n.c. n.c. n.c. n.c. dq 15 /a -1 dq 8 dq 9 dq 10 dq 11 a 16 byte v ss dq 14 dq 13 dq 5
7 mbm29f200ta -70/-90/-12 /mbm29f200ba -70/-90/-12 n logic symbol table 1 mbm29f200ta/ba pin con?uration pin function a -1 , a 0 to a 16 address inputs dq 0 to dq 15 data inputs/outputs ce chip enable oe output enable we write enable ry/by ready-busy output reset hardware reset pin/sector protection unlock byte selects 8-bit or 16-bit mode n.c. no internal connection v ss device ground v cc device power supply (5.0 v 10%) 17 a 0 to a 16 we oe ce dq 0 to dq 15 16 or 8 reset ry/by a -1 byte
8 mbm29f200ta -70/-90/-12 /mbm29f200ba -70/-90/-12 n ordering information standard products fujitsu standard products are available in several packages. the order number is formed by a combination of: mbm29f200 ta -70 pftn device number/description mbm29f200 2 mega-bit (256k 8-bit or 128k 16-bit) cmos flash memory 5.0 v-only read, write, and erase package type pftn = 48-pin thin small outline package (tsop) standard pinout pftr = 48-pin thin small outline package (tsop) reverse pinout pf = 44-pin small outline package speed option see product selector guide boot code sector architecture t = top sector b = bottom sector
9 mbm29f200ta -70/-90/-12 /mbm29f200ba -70/-90/-12 legend: l = v il , h = v ih , x = v il or v ih , = pulse input. see dc characteristics for voltage levels. notes: 1. manufacturer and device codes may also be accessed via a command register write sequence. refer to table 7. 2. refer to the section on sector protection. 3. we can be v il if oe is v il , oe at v ih initiates the write operations. table 2 mbm29f200ta/ba user bus operations (byte = v ih ) operation ce oe we a 0 a 1 a 6 a 9 dq 0 to dq 15 reset auto-select manufacturer code (1) l l h l l l v id code h auto-select device code (1) l l h h l l v id code h read (3) l l h a 0 a 1 a 6 a 9 d out h standby h xxxxxx high-z h output disable l h h xxxx high-z h write l h l a 0 a 1 a 6 a 9 d in h enable sector protection (2) l v id xxlv id xh verify sector protection (2) l lhlhlv id code h temporary sector unprotection xxxxxxx x v id reset (hardware)/standby xxxxxxx high-z l table 3 mbm29f200ta/ba user bus operations (byte = v il ) operation ce oe we dq 15 /a -1 a 0 a 1 a 6 a 9 dq 0 to dq 7 reset auto-select manufacturer code (1) l l h x l l l v id code h auto-select device code (1) l l h x h l l v id code h read (3) l l h a -1 a 0 a 1 a 6 a 9 d out h standby h xxxxxxx high-z h output disable l h h xxxxx high-z x write l h l a -1 a 0 a 1 a 6 a 9 d in h enable sector protection (2) l v id xxxlv id xh verify sector protection (2) l l h x l h l v id code h temporary sector unprotection xxxxxxxx x v id reset (hardware)/standby xxxxxxxx high-z l
10 mbm29f200ta -70/-90/-12 /mbm29f200ba -70/-90/-12 read mode the mbm29f200ta/ba has two control functions which must be satis?d in order to obtain data at the outputs. ce is the power control and should be used for a device selection. oe is the output control and should be used to gate data to the output pins if a device is selected. address access time (t acc ) is equal to the delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from stable addresses and stable ce to valid data at the output pins. the output enable access time is the delay from the falling edge of oe to valid data at the output pins (assuming the addresses have been stable for at least t acc -t oe time). standby mode there are two ways to implement the standby mode on the mbm29f200ta/ba devices, one using both the ce and reset pins; the other via the reset pin only. when using both pins, a cmos standby mode is achieved with ce and reset inputs both held at v cc 0.3 v. under this condition the current is typically reduced to less than 100 m a. a ttl standby mode (ce and reset pins held at v ih ), when the current required is reduced to approximately 1 ma. the device can be read with standard access time (t ce ) from either of these standby modes. when using the reset pin only, a cmos standby mode is achieved with reset input held at v ss 0.3 v (ce = ? or ??. under this condition the current is consumed is less than 100 m a. a ttl standby mode (reset pin held at v il (ce = ? or ??, when the current required is reduced to approximately 1 ma. once the reset pin is taken high, the device requires 500 ns of wake up time before outputs are valid for read access. in the standby mode the outputs are in the high impedance state, independent of the oe input. output disable with the oe input at a logic high level (v ih ), output from the device is disabled. this will cause the output pins to be in a high impedance state. autoselect the autoselect mode allows the reading out of a binary code from the device and will identify its manufacturer and type. this mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. this mode is functional over the entire temperature range of the device. to activate this mode, the programming equipment must force v id (11.5 v to 12.5 v) on address pin a 9 . two identi?r bytes may then be sequenced from the device outputs by toggling address a 0 from v il to v ih . all addresses are don? cares except a 0 , a 1 , and a 6 . the manufacturer and device codes may also be read via the command register, for instances when the mbm29f200ta/ba is erased or programmed in a system without access to high voltage on the a 9 pin. the command sequence is illustrated in table 7 (refer to autoselect command section). a 0 = v il represents the manufacturers code (fujitsu = 04h) and a 0 = v ih the device identi?r code (mbm29f200ta = 51h and mbm29f200ba = 57h for 8 mode; mbm29f200ta = 2251h and mbm29f200ba = 2257h for 16 mode). all identi?es for manufacturer and device will exhibit odd parity with dq 7 de?ed as the parity bit. in order to read the proper device codes when executing the autoselect, a 1 must be v il (see tables 4.1 and 4.2).
11 mbm29f200ta -70/-90/-12 /mbm29f200ba -70/-90/-12 * : outputs 01h at protected sector addresses and outputs 00h at unprotected sector addresses. (b): byte mode (w): word mode write device erasure and programming are accomplished via the command register. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. the command register itself does not occupy any addressable memory location. the register is a latch used to store the commands, along with the address and data information needed to execute the command. the command register is written by bringing we to v il , while ce is at v il and oe is at v ih . addresses are latched on the falling edge of we or ce , whichever happens later; while data is latched on the rising edge of we or ce , whichever happens ?st. standard microprocessor write timings are used. refer to ac write characteristics and the erase/programming waveforms for speci? timing parameters. sector protection the mbm29f200ta/ba features hardware sector protection. this feature will disable both program and erase operations in any number of sectors (0 through 6). the sector protection feature is enabled using programming equipment at the user's site. the device is shipped with all sectors unprotected. to activate this mode, the programming equipment must force v id on address pin a 9 and control pin oe , (suggest v id = 11.5 v), ce = v il , and a 6 = v il . the sector addresses (a 16 , a 15 , a 14 , a 13 , and a 12 ) should be set to the sector to be protected. tables 5 and 6 de?e the sector address for each of the seven (7) individual sectors. programming of the protection circuitry begins on the falling edge of the we pulse and is terminated with the rising edge of the same. sector addresses must be held constant during the we pulse. refer to ?ures 14 and 20 for sector protection waveforms and algorithm. table 4 .1 mbm29f200ta/ba sector protection verify autoselect codes type a 12 to a 16 a 6 a 1 a 0 code (hex) manufacturers code x v il v il v il 04h mbm29f200a device code mbm29f200ta byte xv il v il v ih 51h word 2251h mbm29f200ba byte xv il v il v ih 57h word 2257h sector protection sector addresses v il v ih v il 01h* table 4 .2 expanded autoselect code table type code dq 15 dq 14 dq 13 dq 12 dq 11 dq 10 dq 9 dq 8 dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 manufacturers code 04h 00000000 00000100 device code mbm29f200ta (b) (w) 51h 2251h a -1 0 hi-z 0 hi-z 1 hi-z 0 hi-z 0 hi-z 0 hi-z 1 hi-z 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 1 1 mbm29f200ba (b) (w) 57h 2257h a -1 0 hi-z 0 hi-z 1 hi-z 0 hi-z 0 hi-z 0 hi-z 1 hi-z 0 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 sector protection 01h 00000000 00000001
12 mbm29f200ta -70/-90/-12 /mbm29f200ba -70/-90/-12 to verify programming of the protection circuitry, the programming equipment must force v id on address pin a 9 with ce and oe at v il and we at v ih . scanning the sector addresses (a 16 , a 15 , a 14 , a 13 , and a 12 ) while (a 6 , a 1 , a 0 ) = (0, 1, 0) will produce a logical ? code at device output dq 0 for a protected sector. otherwise the device will produce 00h for unprotected sector. in this mode, the lower order addresses, except for a 0 , a 1 , and a 6 are don't care. address locations with a 1 = v il are reserved for autoselect manufacturer and device codes. it is also possible to determine if a sector is protected in the system by writing an autoselect command. performing a read operation at the address location xx02h, where the higher order addresses (a 16 , a 15 , a 14 , a 13 , and a 12 ) are the sector address will produce a logical ? at dq 0 for a protected sector. see table 4.1 and 4.2 for autoselect codes. temporary sector unprotection this feature allows temporary unprotection of previously protected sectors of the mbm29f200ta/ba device in order to change data. the sector unprotection mode is activated by setting the reset pin to high voltage (12 v). during this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. once the 12 v is taken away from the reset pin, all the previously protected sectors will be protected again.
13 mbm29f200ta -70/-90/-12 /mbm29f200ba -70/-90/-12 table 5 sector address tables (mbm29f200ta) sector address a 16 a 15 a 14 a 13 a 12 address range sa0 0 0 x x x 00000h to 0ffffh sa1 0 1 x x x 10000h to 1ffffh sa2 1 0 x x x 20000h to 2ffffh sa3 1 1 0 x x 30000h to 37fffh sa411100 38000h to 39fffh sa511101 3a000h to 3bfffh sa61111x 3c000h to 3ffffh table 6 sector address tables (mbm29f200ba) sector address a 16 a 15 a 14 a 13 a 12 address range sa00000x 00000h to 03fffh sa100010 04000h to 05fffh sa200011 06000h to 07fffh sa3 0 0 1 x x 08000h to 0ffffh sa4 0 1 x x x 10000h to 1ffffh sa5 1 0 x x x 20000h to 2ffffh sa6 1 1 x x x 30000h to 3ffffh
14 mbm29f200ta -70/-90/-12 /mbm29f200ba -70/-90/-12 notes: 1. address bits a 15 and a 16 = x = h or l for all address commands except for program address (pa) and sector address (sa). 2. bus operations are de?ed in table 2 and 3. 3. ra =address of the memory location to be read. pa = address of the memory location to be programmed. addresses are latched on the falling edge of the we pulse. sa =address of the sector to be erased. the combination of a 16 , a 15 , a 14 , a 13 , and a 12 will uniquely select any sector. 4. rd =data read from location ra during read operation. pd =data to be programmed at location pa. data is latched on the falling edge of we . 5. the system should generate the following address patterns: word mode: 5555h or 2aaah to addresses a 0 to a 14 byte mode: aaaah or 5555h to addresses a ? to a 14 6. both read/reset commands are functionally equivalent, resetting the device to the read mode. * : either of the two reset commands will reset the device. command de?itions device operations are selected by writing speci? address and data sequences into the command register. writing incorrect address and data values or writing them in the improper sequence will reset the device to read mode. table 7 de?es the valid register command sequences. note that the erase suspend (b0h) and erase resume (30h) commands are valid only while the sector erase operation is in progress. moreover both read/ reset commands are functionally equivalent, resetting the device to the read mode. please note that commands are always written at dq 0 to dq 7 and dq 8 to dq 15 bits are ignored. read/reset command the read or reset operation is initiated by writing the read/reset command sequence into the command register. microprocessor read cycles retrieve array data from the memory. the device remains enabled for reads until the command register contents are altered. table 7 mbm29f200ta/ba command de?itions command sequence bus write cycles req? first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle addr. data addr. data addr. data addr. data addr. data addr. data read/reset* word 1 xxxh f0h byte read/reset* word 3 5555h aah 2aaah 55h 5555h f0hrard byte aaaah 5555h aaaah autoselect word 3 5555h aah 2aaah 55h 5555h 90h byte aaaah 5555h aaaah program word 4 5555h aah 2aaah 55h 5555h a0hpapd byte aaaah 5555h aaaah chip erase word 6 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h 5555h 10h byte aaaah 5555h aaaah aaaah 5555h aaaah sector erase word 6 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h sa 30h byte aaaah 5555h aaaah aaaah 5555h sector erase suspend erase can be suspended during sector erase with addr (? or ??. data (b0h) sector erase resume erase can be resumed after suspend with addr (? or ??. data (30h)
15 mbm29f200ta -70/-90/-12 /mbm29f200ba -70/-90/-12 the device will automatically power-up in the read/reset state. in this case, a command sequence is not required to read data. standard microprocessor read cycles will retrieve array data. this default value ensures that no spurious alteration of the memory content occurs during the power transition. refer to the ac read characteristics and waveforms for the speci? timing parameters. autoselect command flash memories are intended for use in applications where the local cpu alters memory contents. as such, manufacture and device codes must be accessible while the device resides in the target system. prom programmers typically access the signature codes by raising a 9 to a high voltage. however, multiplexing high voltage onto the address lines is not generally desired system design practice. the device contains an autoselect command operation to supplement traditional prom programming methodology. the operation is initiated by writing the autoselect command sequence into the command register. following the command write, a read cycle from address xx00h retrieves the manufacture code of 04h. a read cycle from address xx01h for 16 (xx02h for 8) returns the device code (mbm29f200ta = 51h and mbm29f200ba = 57h for 8 mode; mbm29f200ta = 2251h and mbm29f200ba = 2257h for 16 mode). (see tables 4.1 and 4.2.) all manufacturer and device codes will exhibit odd parity with dq 7 de?ed as the parity bit. sector state (protection or unprotection) will be informed by address xx02h for 16 (xx04h for 8). scanning the sector addresses (a 16 , a 15 , a 14 , a 13 and a 12 ) while (a 6 , a 1 , a 0 ) = (0, 1, 0) will produce a logical ? at device output dq 0 for a protected sector. to terminate the operation, it is necessary to write the read/reset command sequence into the register, and also to write the autoselect command during the operation, execute it after writing read/reset command sequence. byte/word programming the device is programmed on a byte-by-byte (or word-by-word) basis. programming is a four bus cycle operation. there are two ?nlock write cycles. these are followed by the program set-up command and data write cycles. addresses are latched on the falling edge of ce or we , whichever happens later and the data is latched on the rising edge of ce or we , whichever happens ?st. the rising edge of ce or we (whichever happens ?st) begins programming. upon executing the embedded program algorithm command sequence, the system is not required to provide further controls or timings. the device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. the automatic programming operation is completed when the data on dq 7 is equivalent to data written to this bit (see write operation status section) at which time the device returns to the read mode and addresses are no longer latched. therefore, the device requires that a valid address to the device be supplied by the system at this particular instance of time. hence, data polling must be performed at the memory location which is being programmed. any commands written to the chip during this period will be ignored. if operating hardware reset during the programming, it is impossible to guarantee the data are being written. programming is allowed in any sequence and across sector boundaries. beware that a data ? cannot be programmed back to a ?? attempting to do so may either hang up the device, or result in an apparent success according to the data polling algorithm but a read from reset/read mode will show that the data is still ?? only erase operations can convert ?? to ??. figure 16 illustrates the embedded programming algorithm using typical command strings and bus operations. chip erase chip erase is a six bus cycle operation. there are two ?nlock write cycles. these are followed by writing the ?et-up command. two more ?nlock write cycles are then followed by the chip erase command. chip erase does not require the user to program the device prior to erase. upon executing the embedded erase algorithm command sequence the device automatically will program and verify the entire memory for an all zero
16 mbm29f200ta -70/-90/-12 /mbm29f200ba -70/-90/-12 data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. the automatic erase begins on the rising edge of the last we pulse in the command sequence and terminates when the data on dq 7 is ? (see write operation status section) at which time the device returns to read the mode. figure 17 illustrates the embedded erase algorithm using typical command strings and bus operations. sector erase sector erase is a six bus cycle operation. there are two ?nlock write cycles. these are followed by writing the ?et-up command. two more ?nlock write cycles are then followed by the sector erase command. the sector address (any address location within the desired sector) is latched on the falling edge of we , while the command (data = 30h) is latched on the rising edge of we . a time-out of 50 m s from the rising edge of the last sector erase command will initiate the sector erase command(s). multiple sectors may be erased concurrently by writing the six bus cycle operations as described above. this sequence is followed with writes of the sector erase command to addresses in other sectors desired to be concurrently erased. the time between writes must be less than 50 m s, otherwise that command will not be accepted and erasure will start. it is recommended that processor interrupts be disabled during this time to guarantee this condition. the interrupts can be re-enabled after the last sector erase command is written. a time-out of 50 m s from the rising edge of the last we will initiate the execution of the sector erase command(s). if another falling edge of the we occurs within the 50 m s time-out window the timer is reset (monitor dq 3 to determine if the sector erase timer window is still open, see section dq 3 , sector erase timer). any command other than sector erase or erase suspend during this time-out period will reset the device to read mode, ignoring the previous command string. resetting the device once execution has begun will corrupt the data in that sector. in that case, restart the erase on those sectors and allow them to complete. (refer to the write operation status section for sector erase timer operation.) loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 6). sector erase does not require the user to program the device prior to erase. the device automatically programs all memory locations in the sector(s) to be erased prior to electrical erase. when erasing a sector or sectors the remaining unselected sectors are not affected. the system is not required to provide any controls or timings during these operations. the automatic sector erase begins after the 50 m s time out from the rising edge of the we pulse for the last sector erase command pulse and terminates when the data on dq 7 is ? (see write operation status section) at which time the device returns to the read mode. data polling must be performed at an address within any of the sectors being erased. figure 17 illustrates the embedded erase algorithm using typical command strings and bus operations. erase suspend the erase suspend command allows the user to interrupt a sector erase operation and then perform data reads (not program) from a non-busy sector. this command is applicable only during the sector erase operation and will be ignored if written during the chip erase or programming operation. the erase suspend command (b0h) will be allowed only during the sector erase operation that will include the sector erase time-out period after the sector erase commands (30h). writing this command during the time-out will result in immediate termination of the time-out period. any subsequent writes of the sector erase command will be taken as the erase resume command. note that any other commands during the time out will reset the device to read mode. the addresses are don't-cares when writing the erase suspend or erase resume commands. when the erase suspend command is written during a sector erase operation, the device will take a maximum of 15 m s to suspend the erase operation. when the device has entered the erase-suspended mode, the ry/by output pin and the dq 7 bit will be at logic ?? and dq 6 will stop toggling. the user must use the address of the erasing sector for reading dq 6 and dq 7 to determine if the erase operation has been suspended. further writes of the erase suspend command are ignored.
17 mbm29f200ta -70/-90/-12 /mbm29f200ba -70/-90/-12 when the erase operation has been suspended, the device defaults to the erase-suspend-read mode. reading data in this mode is the same as reading from the standard read mode except that the data must be read from sectors that have not been erase-suspended. to resume the operation of sector erase, the resume command (30h) should be written. any further writes of the resume command at this point will be ignore. another erase suspend command can be written after the chip has resumed erasing. write operation status notes: 1. dq 0 , dq 1 , dq 2 are reserve pins for future use. 2. dq 8 to dq 15 = don? care for 16 mode. 3. dq 4 is for fujitsu internal use only. dq 7 data polling the mbm29f200ta/ba device features data polling as a method to indicate to the host that the embedded algorithms are in progress or completed. during the embedded program algorithm an attempt to read the device will produce the complement of the data last written to dq 7 . upon completion of the embedded program algorithm, an attempt to read the device will produce the true data last written to dq 7 . during the embedded erase algorithm, an attempt to read the device will produce a ? at the dq 7 output. upon completion of the embedded erase algorithm an attempt to read the device will produce a ? at the dq 7 output. the ?wchart for data polling (dq 7 ) is shown in figure 18. for chip erase, the data polling is valid after the rising edge of the sixth we pulse in the six write pulse sequence. for sector erase, the data polling is valid after the last rising edge of the sector erase we pulse. data polling must be performed at sector address within any of the sectors being erased and not a protected sector. otherwise, the status may not be valid. once the embedded algorithm operation is close to being completed, the mbm29f200ta/ba data pins (dq 7 ) may change asynchronously while the output enable (oe ) is asserted low. this means that the device is driving status information on dq 7 at one instant of time and then that byte's valid data at the next instant of time. depending on when the system samples the dq 7 output, it may read the status or valid data. even if the device has completed the embedded algorithm operation and dq 7 has a valid data, the data outputs on dq 0 to dq 6 may be still invalid. the valid data on dq 0 to dq 7 will be read on the successive read attempts. the data polling feature is only active during the embedded programming algorithm, embedded erase algorithm, or sector erase time-out (see table 8). see figure 8 for the data polling timing speci?ations and diagrams. table 8 hardware sequence flags status dq 7 dq 6 dq 5 dq 3 dq 2 to dq 0 in progress embedded program algorithm dq 7 toggle 0 0 (d ) (note 1) embedded erase algorithm 0 toggle 0 1 erase suspended mode erase suspend read (erase suspended sector) 1101 erase suspend read (non-erase suspended sector) data data data data exceeded time limits embedded program algorithm dq 7 toggle 1 0 program/erase in embedded erase algorithm 0 toggle 1 1
18 mbm29f200ta -70/-90/-12 /mbm29f200ba -70/-90/-12 dq 6 toggle bit the mbm29f200ta/ba also features the ?oggle bit as a method to indicate to the host system that the embedded algorithms are in progress or completed. during an embedded program or erase algorithm cycle, successive attempts to read (oe toggling) data from the device will result in dq 6 toggling between one and zero. once the embedded program or erase algorithm cycle is completed, dq 6 will stop toggling and valid data will be read on the next successive attempts. during programming, the toggle bit is valid after the rising edge of the fourth we pulse in the four write pulse sequence. for chip erase, the toggle bit is valid after the rising edge of the sixth we pulse in the six write pulse sequence. for sector erase, the toggle bit is valid after the last rising edge of the sector erase we pulse. the toggle bit is active during the sector time out. in programming, if the sector being written to is protected, the toggle bit will toggle for about 2 m s and then stop toggling without the data having changed. in erase, the device will erase all the selected sectors except for the ones that are protected. if all selected sectors are protected, the chip will toggle the toggle bit for about 100 m s and then drop back into read mode, having changed none of the data. either ce or oe toggling will cause the dq 6 to toggle. in addition, an erase suspend/resume command will cause dq 6 to toggle. see figure 9 for the toggle bit timing speci?ations and diagrams. dq 5 exceeded timing limits dq 5 will indicate if the program or erase time has exceeded the speci?d limits (internal pulse count). under these conditions dq 5 will produce a ?? this is a failure condition which indicates that the program or erase cycle was not successfully completed. data polling is the only operating function of the device under this condition. the ce circuit will partially power down the device under these conditions (to approximately 2 ma). the oe and we pins will control the output disable functions as described in tables 2 and 3. the dq 5 failure condition may also appear if a user tries to program a non blank location without erasing. in this case the device locks out and never completes the embedded algorithm operation. hence, the system never reads a valid data on dq 7 bit and dq 6 never stops toggling. once the device has exceeded timing limits, the dq 5 bit will indicate a ?. please note that this is not a device failure condition since the device was incorrectly used. dq 3 sector erase timer after the completion of the initial sector erase command sequence the sector erase time-out will begin. dq 3 will remain low until the time-out is complete. data polling and toggle bit are valid after the initial sector erase command sequence. if data polling or the toggle bit indicates the device has been written with a valid erase command, dq 3 may be used to determine if the sector erase timer window is still open. if dq 3 is high (?? the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by data polling or toggle bit. if dq 3 is low (??, the device will accept additional sector erase commands. to insure the command has been accepted, the system software should check the status of dq 3 prior to and following each subsequent sector erase command. if dq 3 were high on the second status check, the command may not have been accepted. refer to table 8: hardware sequence flags.
19 mbm29f200ta -70/-90/-12 /mbm29f200ba -70/-90/-12 ry/by ready/busy the mbm29f200ta/ba provides a ry/by open-drain output pin as a way to indicate to the host system that the embedded algorithms are either in progress or completed. if the output is low, the device is busy with either a program or erase operation. if the output is high, the device is ready to accept any read/write or erase operation. when the ry/by pin is low, the device will not accept any additional program or erase commands. if the mbm29f200ta/ba is placed in an erase suspend mode, the ry/by output will be high. also, since this is an open-drain output, many ry/by pins can be tied together in parallel with a pull up resistor to v cc . during programming, the ry/by pin is driven low after the rising edge of the fourth we pulse. during an erase operation, the ry/by pin is driven low after the rising edge of the sixth we pulse. the ry/by pin will indicate a busy condition during the reset pulse. refer to figures 10 and 11 for a detailed timing diagram. reset hardware reset the mbm29f200ta/ba device may be reset by driving the reset pin to v il . the reset pin has a pulse requirement and has to be kept low (v il ) for at least 500 ns in order to properly reset the internal state machine. any operation in the process of being executed will be terminated and the internal state machine will be reset to the read mode 20 m s after the reset pin is driven low. furthermore, once the reset pin goes high, the device requires an additional 50 ns before it will allow read access. when the reset pin is low, the device will be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. if a hardware reset occurs during a program or erase operation, the data at that particular location will be corrupted. please note that the ry/by output signal should be ignored during the reset pulse. refer to figure 11 for the timing diagram. refer to temporary sector unprotection for additional functionality. if hardware reset occurs during embedded erase algorithm, there is a possibility that the erasing sector(s) cannot be used. byte/word con?uration the byte pin selects the byte (8-bit) mode or word (16 bit) mode for the mbm29f200ta/ba device. when this pin is driven high, the device operates in the word (16 bit) mode. the data is read and programmed at dq 0 to dq 15 . when this pin is driven low, the device operates in byte (8 bit) mode. under this mode, the dq 15 /a -1 pin becomes the lowest address bit and dq 8 to dq 14 bits are tri-stated. however, the command bus cycle is always an 8-bit operation and hence commands are written at dq 0 to dq 7 and the dq 8 to dq 15 bits are ignored. refer to figures 12 and 13 for the timing diagram. data protection the mbm29f200ta/ba is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. during power up the device automatically resets the internal state machine in the read mode. also, with its control register architecture, alteration of the memory contents only occurs after successful completion of speci? multi-bus cycle command sequences. the device also incorporates several features to prevent inadvertent write cycles resulting form v cc power-up and power-down transitions or system noise. low v cc write inhibit to avoid initiation of a write cycle during v cc power-up and power-down, a write cycle is locked out for v cc less than 3.2 v (typically 3.7 v). if v cc < v lko , the command register is disabled and all internal program/erase circuits are disabled. under this condition the device will reset to the read mode. subsequent writes will be ignored until the v cc level is greater than v lko . it is the users responsibility to ensure that the control pins are logically correct to prevent unintentional writes when v cc is above 3.2 v. if embedded erase algorithm is interrupted, there is possibility that the erasing sector(s) cannot be used.
20 mbm29f200ta -70/-90/-12 /mbm29f200ba -70/-90/-12 write pulse ?litch protection noise pulses of less than 5 ns (typical) on oe , ce , or we will not initiate a write cycle. logical inhibit writing is inhibited by holding any one of oe = v il , ce = v ih , or we = v ih . to initiate a write cycle ce and we must be a logical zero while oe is a logical one. power-up write inhibit power-up of the device with we = ce =v il and oe = v ih will not accept commands on the rising edge of we . the internal state machine is automatically reset to the read mode on power-up.
21 mbm29f200ta -70/-90/-12 /mbm29f200ba -70/-90/-12 n absolute maximum ratings storage temperature .................................................................................................. ?5 c to +125 c ambient temperature with power applied................................................................... ?5 c to +85 c voltage with respect to ground all pins except a 9 , oe , reset (note 1).................. ?.0 v to +7.0 v v cc (note 1) ................................................................................................................ ?.0 v to +7.0 v a 9 , oe , reset (note 2) ............................................................................................. ?.0 v to +13.5 v notes: 1. minimum dc voltage on input or i/o pins is ?.5 v. during voltage transitions, inputs may negative overshoot v ss to ?.0 v for periods of up to 20 ns. maximum dc voltage on output and i/o pins is v cc +0.5 v. during voltage transitions, outputs may positive overshoot to v cc +2.0 v for periods of up to 20 ns. 2. minimum dc input voltage on a 9 , oe , reset pins are ?.5 v. during voltage transitions, a 9 , oe , reset pins may negative overshoot v ss to ?.0 v for periods of up to 20 ns. maximum dc input voltage on a 9 , oe , reset pins are +13.0 v which may positive overshoot to 13.5 v for periods of up to 20 ns. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n recomended operating ranges commercial devices ambient temperature (ta) ........................................................................?0 c to +70 c v cc supply voltages ..................................................................................+4.50 v to +5.50 v operating ranges de?e those limits between which the functionality of the device is guaranteed. warning: recommended operating conditions are normal operating ranges for the semiconductor device. all the devices electrical characteristics are warranted when operated within these ranges. always use semiconductor devices within the recommended operating conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representative beforehand.
22 mbm29f200ta -70/-90/-12 /mbm29f200ba -70/-90/-12 n maximum overshoot figure 1 maximum negative overshoot waveform +0.8 v ?.5 v 20 ns ?.0 v 20 ns 20 ns figure 2 maximum positive overshoot waveform +2.0 v v cc +0.5 v 20 ns v cc +2.0 v 20 ns 20 ns figure 3 maximum positive overshoot waveform v cc +0.5 v +13.0 v 20 ns +14.0 v 20 ns 20 ns * : this waveform is applied for a 9 , oe , and reset .
23 mbm29f200ta -70/-90/-12 /mbm29f200ba -70/-90/-12 n dc characteristics ttl/nmos compatible notes: 1. the i cc current listed includes both the dc operating current and the frequency dependent component (at 6 mhz). the frequency component typically is 2 ma/mhz. 2. i cc active while embedded algorithm (program or erase) is in progress. 3. applicable to sector protection function. parameter symbol parameter description test conditions min. max. unit i li input leakage current v in = v ss to v cc , v cc = v cc max. 1.0 m a i lo output leakage current v out = v ss to v cc , v cc = v cc max. 1.0 m a i lit a 9 , oe , reset inputs leakage current v cc = v cc max., a 9 , oe , reset = 12.0 v ?0 m a i cc1 v cc active current (note 1) ce = v il , oe = v ih byte 35 ma word 40 i cc2 v cc active current (note 2) ce = v il , oe = v ih ?0ma i cc3 v cc current (standby) v cc = v cc max., ce = v ih , reset = v ih 1.0 ma i cc4 v cc current (standby, reset) v cc = v cc max., reset = v il 1.0 ma v il input low level ?.5 0.8 v v ih input high level 2.0 v cc +0.5 v v id voltage for autoselect and sector protection (a 9 , oe , reset ) (note 3) v cc = 5.0 v 11.5 12.5 v v ol output low voltage level i ol = 5.8 ma, v cc = v cc min. 0.45 v v oh output high voltage level i oh = ?.5 ma, v cc = v cc min. 2.4 v v lko low v cc lock-out voltage 3.2 4.2 v
24 mbm29f200ta -70/-90/-12 /mbm29f200ba -70/-90/-12 cmos compatible notes: 1. the i cc current listed includes both the dc operating current and the frequency dependent component (at 6 mhz). the frequency component typically is 2 ma/mhz. 2. i cc active while embedded algorithm (program or erase) is in progress. 3. applicable to sector protection function. parameter symbol parameter description test conditions min. max. unit i li input leakage current v in = v ss to v cc , v cc = v cc max. 1.0 m a i lo output leakage current v out = v ss to v cc , v cc = v cc max. 1.0 m a i lit a 9 , oe , reset inputs leakage current v cc = v cc max. a 9 , oe , reset = 12.0 v ?0 m a i cc1 v cc active current (note 1) ce = v il , oe = v ih byte 35 ma word 40 i cc2 v cc active current (note 2) ce = v il , oe = v ih ?0ma i cc3 v cc current (standby) v cc = v cc max., ce = v cc 0.3 v, reset = v cc 0.3 v 100 m a i cc4 v cc current (standby, reset) v cc = v cc max., reset = v ss 0.3 v 100 m a v il input low level ?.5 0.8 v v ih input high level 0.7 v cc v cc +0.3 v v id voltage for autoselect and sector protection (a 9 , oe , reset ) (note 3) v cc = 5.0 v 11.5 12.5 v v ol output low voltage level i ol = 5.8 ma, v cc = v cc min. 0.45 v v oh1 output high voltage level i oh = ?.5 ma, v cc = v cc min. 0.85 v cc ? v oh2 i oh = ?00 m a, v cc = v cc min. v cc ?.4 v v lko low v cc lock-out voltage 3.2 4.2 v
25 mbm29f200ta -70/-90/-12 /mbm29f200ba -70/-90/-12 n ac characteristics read only operations characteristics parameter symbols description test setup ?0 (note 1) ?0 (note 2) ?2 (note 2) unit jedec standard t avav t rc read cycle time min. 70 90 120 ns t avqv t acc address to output delay ce = v il oe = v il max. 70 90 120 ns t elqv t ce chip enable to output delay oe = v il max. 70 90 120 ns t glqv t oe output enable to output delay max. 30 35 50 ns t ehqz t df chip enable to output high-z max. 20 20 30 ns t ghqz t df output enable to output high-z max. 20 20 30 ns t axqx t oh output hold time from addresses, ce or oe , whichever occurs first min. 0 0 0 ns ? ready reset pin low to read mode max. 20 20 20 m s t elfl t elfh ce or byte switching low or high max. 5 5 5 ns figure 4 test conditions c l 5.0 v diodes = in3064 or equivalent 2.7 k w device under test in3064 or equivalent 6.2 k w note: c l = 100 pf including jig capaciance 1. test conditions: output load: 1 ttl gate and 100 pf input rise and fall times: 5 ns input pulse levels: 0.0 v to 3.0 v timing measurement reference level input: 1.5 v output: 1.5 v notes: 2. test conditions: output load: 1 ttl gate and 100 pf input rise and fall times: 20 ns input pulse levels: 0.45 v to 2.4 v timing measurement reference level input: 0.8 v and 2.0 v output: 0.8 v and 2.0
26 mbm29f200ta -70/-90/-12 /mbm29f200ba -70/-90/-12 write/erase/program operations alternate we controlled writes notes: 1. this does not include the preprogramming time. 2. applicable to sector protection function. parameter symbols description ?0 ?0 ?2 unit jedec standard t avav t wc write cycle time min. 70 90 120 ns t avwl t as address setup time min. 0 0 0 ns t wlax t ah address hold time min. 45 45 50 ns t dvwh t ds data setup time min. 30 45 50 ns t whdx t dh data hold time min. 0 0 0 ns ? oes output enable setup time min. 0 0 0 ns ? oeh output enable hold time read min. 0 0 0 ns toggle and data polling min. 10 10 10 ns t ghwl t ghwl read recover time before write min. 0 0 0 ns t elwl t cs ce setup time min. 0 0 0 ns t wheh t ch ce hold time min. 0 0 0 ns t wlwh t wp write pulse width min. 35 45 50 ns t whwl t wph write pulse width high min. 20 20 20 ns t whwh1 t whwh1 byte programming operation typ. 8 8 8 m s t whwh2 t whwh2 sector erase operation (note 1) typ. 1 1 1 sec max. 15 15 15 sec ? vcs v cc setup time min. 50 50 50 m s ? vlht voltage transition time (note 2) min. 4 4 4 m s ? wpp write pulse width (note 2) min. 100 100 100 m s ? oesp oe setup time to we active (note 2) min. 4 4 4 m s ? csp ce setup time to we active (note 2) min. 4 4 4 m s ? rp reset pulse width min. 500 500 500 ns ? flqz byte switching low to output high-z max. 20 30 30 ns ? busy program/erase valid to ry/by delay min. 30 35 50 ns
27 mbm29f200ta -70/-90/-12 /mbm29f200ba -70/-90/-12 write/erase/program operations alternate ce controlled writes note: this does not include the preprogramming time. parameter symbols description ?0 ?0 ?2 unit jedec standard t avav t wc write cycle time min. 70 90 120 ns t avel t as address setup time min. 0 0 0 ns t elax t ah address hold time min. 45 45 50 ns t dveh t ds data setup time min. 30 45 50 ns t ehdx t dh data hold time min. 0 0 0 ns ? oes output enable setup time min. 0 0 0 ns ? oeh output enable hold time read min. 0 0 0 ns toggle and data polling min. 10 10 10 ns t ghel t ghel read recover time before write min. 0 0 0 ns t wlel t ws we setup time min. 0 0 0 ns t ehwh t wh we hold time min. 0 0 0 ns t eleh t cp ce pulse width min. 35 45 50 ns t ehel t cph ce pulse width high min. 20 20 20 ns t whwh1 t whwh1 byte programming operation typ. 8 8 8 m s t whwh2 t whwh2 sector erase operation (note) typ. 1 1 1 sec max. 15 15 15 sec ? vcs v cc setup time typ. 50 50 50 m s ? rp reset pulse width min. 500 500 500 ns ? flqz byte switching low to output high-z max. 20 30 30 ns ? busy program/erase valid to ry/by delay min. 30 35 50 ns
28 mbm29f200ta -70/-90/-12 /mbm29f200ba -70/-90/-12 n switching waveforms key to switching waveforms figure 4 ac waveforms for read operations waveform inputs outputs must be steady may change from h to l may change from l to h h or l, any change permitted does not apply will be steady will be changing from h to l will be changing from l to h changing, state unknown center line is high- impedance ?ff?state we oe ce t acc (t df ) (t oh ) (t ce ) t oe outputs t rc addresses addresses stable high-z output valid high-z t oeh
29 mbm29f200ta -70/-90/-12 /mbm29f200ba -70/-90/-12 notes: 1. pa is address of the memory location to be programmed. 2. pd is data to be programmed at byte address. 3. dq 7 is the output of the complement of the data written to the device. 4. d out is the output of the data written to the device. 5. figure indicates last two bus cycles out of four bus cycle sequence. 6. these waveforms are for the 16 mode. figure 5 alternate we controlled program operation timings t ghwl t wp t df t ds t whwh1 t wc t ah 5.0 v ce oe t rc addresses data t as t oe t wph t cs t dh dq 7 pd a0h d out t ce we 5555h pa pa t oh data polling 3rd bus cycle
30 mbm29f200ta -70/-90/-12 /mbm29f200ba -70/-90/-12 figure 6 alternate ce controlled program operation timings notes: 1. pa is address of the memory location to be programmed. 2. pd is data to be programmed at byte address. 3. dq 7 is the output of the complement of the data written to the device. 4. d out is the output of the data written to the device. 5. figure indicates last two bus cycles out of four bus cycle sequence. 6. these waveforms are for the 16 mode. t cp t ds t whwh1 t wc t ah 5.0 v we oe addresses data t as t cph t ws t dh dq 7 pd a0h d out ce 5555h pa pa data polling t ghel t wh
31 mbm29f200ta -70/-90/-12 /mbm29f200ba -70/-90/-12 figure 7 ac waveforms chip/sector erase operations notes: 1. sa is the sector address for sector erase. addresses = 5555h (word), aaaah (byte) for chip erase. 2. these waveforms are for the 16 mode. the addresses differ from 8 mode. t ghwl t ds v cc ce oe addresses data t dh aah we t ah 2aaah 5555h 5555h 2aaah sa t wph t cs t wp t vcs t as 5555h 55h 80h aah 55h 10h/ 30h
32 mbm29f200ta -70/-90/-12 /mbm29f200ba -70/-90/-12 figure 8 ac waveforms for data polling during embedded algorithm operations * : dq 7 = valid data (the device has completed the embedded operation). t oeh t oe t whwh1 or 2 ce oe t oh we dq 7 t df t ch t ce high-z dq 7 = valid data dq 0 to dq 6 dq 0 to dq 6 = invalid dq 0 to dq 6 valid data t oe dq 7 * high-z figure 9 ac waveforms for toggle bit during embedded algorithm operations * : dq 6 = stops toggling (the device has completed the embedded operation). t oeh ce we oe data dq 6 = toggle * t oes t oe (dq 0 to dq 7 ) dq 6 = stop toggling dq 0 to dq 7 valid dq 6 = toggle
33 mbm29f200ta -70/-90/-12 /mbm29f200ba -70/-90/-12 figure 10 ry/by timing diagram during program/erase operations ce we ry/by the rising edge of the last we signal entire programming or erase operations t busy figure 11 reset /ry/by timing diagram ce reset ry/by t rp t ready
34 mbm29f200ta -70/-90/-12 /mbm29f200ba -70/-90/-12 figure 13 byte timing diagram for read operations ce oe byte dq 0 to dq 14 dq 15 /a -1 t elfl t elfh t flqz data output (dq 0 to dq 14 ) data output (dq 0 to dq 7 ) dq 15 output address input figure 14 byte timing diagram for write operations ce we byte the falling edge of the last we signal t hold (t ah ) t set (t as )
35 mbm29f200ta -70/-90/-12 /mbm29f200ba -70/-90/-12 figure 15 ac waveforms for sector protection t vlht sax = sector address for initial sector sax a 16 to a 12 say a 0 a 1 a 9 12 v 5 v t vlht oe 12 v 5 v t vlht t oesp t wpp we ce t oe 01h data say = sector address for next sector a 6 t csp
36 mbm29f200ta -70/-90/-12 /mbm29f200ba -70/-90/-12 figure 16 temporary sector unprotection ce we ry/by reset 12 v 5 v program or erase command sequence 5 v t vlht
37 mbm29f200ta -70/-90/-12 /mbm29f200ba -70/-90/-12 * : device is either powered-down, erase inhibit or program inhibit. table 9 embedded programming algorithm bus operations command sequence comments standby* write program valid address/data sequence read data polling to verify programming standby* compare data output to data expected figure 17 embedded programming algorithm embedded algorithms * : the sequence is applied for 16 mode. the addresses differ from 8 mode. no yes program command sequence* (address/command): 5555h/aah 2aaah/55h 5555h/a0h write program command sequence (see below) data polling device increment address last address ? programming completed program address/program data start
38 mbm29f200ta -70/-90/-12 /mbm29f200ba -70/-90/-12 * : device is either powered-down, erase inhibit or program inhibit. table 10 embedded erase algorithm bus operations command sequence comments standby* write erase read data polling to verify erasure standby* compare output to ffh figure 18 embedded erase algorithm embedded algorithms * : the sequence is applied for 16 mode. the addresses differ from 8 mode. start 5555h/aah 2aaah/55h 5555h/aah 5555h/80h 5555h/10h 2aaah/55h 5555h/aah 2aaah/55h 5555h/aah 5555h/80h 2aaah/55h additional sector erase commands are optional. write erase command sequece (see below) data polling or toggle bit successfully completed erasure completed chip erase command sequence* (address/command): individual sector/multiple sector* erase command sequence (address/command): sector address/30h sector address/30h sector address/30h
39 mbm29f200ta -70/-90/-12 /mbm29f200ba -70/-90/-12 figure 19 data polling algorithm note: dq 7 is rechecked even if dq 5 = ? because dq 7 may change simultaneously with dq 5 . va = address for programming = any of the sector addresses within the sector being erased during sector erase operation = xxxxh during chip erase fail dq 7 = data ? no no dq 7 = data ? dq 5 = 1? pass yes yes yes no read byte (dq 0 to dq 7 ) addr. = va read byte (dq 0 to dq 7 ) addr. = va start
40 mbm29f200ta -70/-90/-12 /mbm29f200ba -70/-90/-12 figure 20 toggle bit algorithm note: dq 6 is rechecked even if dq 5 = ? because dq 6 may stop toggling at the same time as dq 5 changing to ?? va = address for programming = any of the sector addresses within the sector being erased during sector erase operation = xxxxh during chip erase = any address not within the sector in the process of an erase suspend operation. dq 6 = toggle ? yes no dq 6 = toggle ? dq 5 = 1? yes no no yes start read byte (dq 0 to dq 7 ) addr. = va read byte (dq 0 to dq 7 ) addr. = va fail pass
41 mbm29f200ta -70/-90/-12 /mbm29f200ba -70/-90/-12 figure 21 sector protection algorithm set up sector group addr. activate we pulse we = v ih , ce = oe = v il , yes no time out 100 m s read from sector remove v id from a 9 write reset command increment plscnt no yes start sector protection completed data = 01h? no yes plscnt = 25? remove v id from a 9 write reset command device failed (a 16 , a 15 , a 14 , a 13 , a 12 ) plscnt = 1 oe = v id , a 9 = v id , a 6 = ce = v il , reset = v ih a 9 should remain v id addr. = sa, a 1 = 1, a 0 = a 6 = 0 protect another sector?
42 mbm29f200ta -70/-90/-12 /mbm29f200ba -70/-90/-12 figure 22 temporary sector unprotection algorithm notes: 1. all protected sectors are unprotected. 2. all previously protected sectors are protected once again. reset = v id reset = v ih start (note 1) perform erase or program operations temporary sector group unprotect completed (note 2)
43 mbm29f200ta -70/-90/-12 /mbm29f200ba -70/-90/-12 n typical characteristics curves 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 4.5 5.0 i cc1 , normalized t a = +25 c f = 6.0 mhz v cc supply voltage (v) 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 i cc1 , normalized f frequency (mhz) 10 0.1 1 read power supply current (i cc1 ) vs. supply voltage read power supply current vs. frequency 45 40 35 30 25 20 15 10 5 0 0 0.2 0.4 0.6 0.8 1 v ol ? level output voltage (v) i ol ? level output current (ma) ??level output current vs. ??level output voltage ?0 ?5 ?0 ?5 ?0 ?5 ?0 ? 0 01 2 345 v oh ? level output voltage (v) i oh ? level output current (ma) ??level output current vs. ??level output voltage 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 t acc vs. supply voltage (v cc ) v cc supply voltage (v) t acc , normalized v cc = 5.0 v t a = +25 c v in = v cc /gnd c l load capacitance (pf) t acc , normalized 5.5 word byte v cc = 5.0 v t a = +25 c t a = +25 c 4.5 5.5 5.0 1.20 1.15 1.10 1.05 1.00 0.95 0.90 0.85 0.80 t acc vs. load capacitance (c l ) 0 20 40 60 80 100 120 v cc = 5.0 v t a = +25 c v cc = 5.0 v t a = +25 c word byte
44 mbm29f200ta -70/-90/-12 /mbm29f200ba -70/-90/-12 (continued) 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0153045 75 t acc vs. ambient temperature t a ambient temperature ( c) t acc , normalized v cc = 5.0 v 60 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 t ce vs. ambient temperature t a ambient temperature ( c) t ce , normalized v cc = 5.0 v 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 t oe , t df vs. ambient temperature t a ambient temperature ( c) t oe , t df , normalized v cc = 5.0 v t oe t df 40 30 20 10 0 current wave form (chip erase) 500 ms/division i cc2 (ma) pre-program erase v ih v il we ?0 ?5 0 15 30 45 75 60 ?0 ?5 0153045 75 60 ?0 ?5
45 mbm29f200ta -70/-90/-12 /mbm29f200ba -70/-90/-12 n erase and programming performance n tsop pin capacitance note: test conditions t a = 25 c, f = 1.0 mhz n sop pin capacitance note: test conditions t a = 25 c, f = 1.0 mhz parameter limits unit comment min. typ. max. sector erase time 1 15 sec excludes 00h programming prior to erasure byte programming time 8 500 m s excludes system-level overhead chip programming time 2.1 13 sec excludes system-level overhead erase/program cycle 100,000 cycles parameter symbol parameter description test setup typ. max. unit c in input capacitance v in = 0 8 9 pf c out output capacitance v out = 0 8 10 pf c in2 control pin capacitance v in = 0 8.5 11.5 pf parameter symbol parameter description test setup typ. max. unit c in input capacitance v in = 0 7.5 9 pf c out output capacitance v out = 0 8 10 pf c in2 control pin capacitance v in = 0 8.5 11 pf
46 mbm29f200ta -70/-90/-12 /mbm29f200ba -70/-90/-12 n package dimensions c 1996 fujitsu limited f48029s-2c-2 details of "a" part 0.15(.006) max 0.35(.014) max 0.15(.006) 0.25(.010) index "a" 18.400.20 (.724.008) 20.000.20 (.787.008) 19.000.20 (.748.008) 0.10(.004) 0.500.10 (.020.004) 0.150.05 (.006.002) 11.50ref (.460) 0.50(.0197) typ 0.200.10 (.008.004) 0.05(0.02)min .043 ?.002 +.004 ?0.05 +0.10 1.10 m 0.10(.004) stand off 1 24 25 48 lead no. * * 12.000.20 (.472.008) 48-pin plastic tsop (fpt-48p-m19) * resin protrusion:(each side:0.15(.006)max) dimensions in mm(inches) (mounting height)
47 mbm29f200ta -70/-90/-12 /mbm29f200ba -70/-90/-12 c 1996 fujitsu limited f48030s-2c-2 details of "a" part 0.15(.006) max 0.35(.014) max 0.15(.006) 0.25(.010) index "a" 18.400.20 (.724.008) 20.000.20 (.787.008) 19.000.20 (.748.008) 0.10(.004) 0.500.10 (.020.004) 0.150.10 (.006.002) 11.50(.460)ref 0.50(.0197) typ 0.200.10 (.008.004) 0.05(0.02)min .043 ?.002 +.004 ?0.05 +0.10 1.10 m 0.10(.004) stand off 1 24 25 48 lead no. * * 12.000.20(.472.008) (mounting height) 48-pin plastic tsop (fpt-48p-m20) * resin protrusion:(each side:0.15(.006)ma x dimensions in mm(inches)
48 mbm29f200ta -70/-90/-12 /mbm29f200ba -70/-90/-12 c 1995 fujitsu limited f44023s-2c-2 "a" index 0.40 +0.10 ?0.05 +.004 ?.002 .016 m ?0.13(.005) 1.27(.050)nom (.006.002) 13.000.10 16.000.20 (.512.004) (.630.008) 0.800.20 (.031.008) 0(0)min 1 22 23 44 lead no. (stand off) 1.120 ?.008 +.010 ?0.20 +0.25 28.45 14.400.20 (.567.008) 0.150.05 0.10(.004) 26.67(1.050)ref 2.50(.098)max dimensions in mm(inches) (mounting height) 44-pin plastic sop (fpt-44p-m16)
49 mbm29f200ta -70/-90/-12 /mbm29f200ba -70/-90/-12 fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-88, japan tel: (044) 754-3763 fax: (044) 754-3329 north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, u.s.a. tel: (408) 922-9000 fax: (408) 432-9044/9045 europe fujitsu mikroelektronik gmbh am siebenstein 6-10 63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 asia paci? fujitsu microelectronics asia pte. limited #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 f9704 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

▲Up To Search▲

Price & Availability of MBM29F200BA12

	To Download MBM29F200BA12 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .